Radio Receiver Front-End ICs at the Sub-THz/THz Frequency Range in Silicon Technology
Thesis event information
Date and time of the thesis defence
Place of the thesis defence
L5, Linnanmaa campus
Topic of the dissertation
Radio Receiver Front-End ICs at the Sub-THz/THz Frequency Range in Silicon Technology
Doctoral candidate
Master of Science Sumit Singh
Faculty and unit
University of Oulu Graduate School, Faculty of Information Technology and Electrical Engineering, CWC-Radio Technologies
Subject of study
Communications Engineering
Opponent
Professor Piet Wambacq, Vrije University Brussels and IMEC Belgium
Custos
Professor Aarno Pärssinen, University of Oulu
High Frequency Electronics for 6G Receiver
Do you know how Albert Einstein once explained the operation of radio? You see, a wire telegraph is a kind of very, very long cat. You pull his tail in New York and his head meows in Los Angeles. Do you understand this? And a radio operates exactly the same way: you send signals here, they receive them there. However, the only difference is that there is no cat.
This thesis represents an endeavor to implement a radio operating at 300 GHz. Why at such a high frequency? Because the higher the frequency, the more bandwidth is available to facilitate ultra-high-speed radio communication. The focus of this work is the design of the front-end of the radio receiver, which is a fascinating fusion of analog circuit theory, microwave theory, and radio frequency engineering. Utilizing the fundamentals of these three domains, I approached the design of the receiver’s front-end.
Modern highly integrated radios are designed using semiconductor technologies. In a typical radio system, information travels through semiconductor material and the atmosphere. Information carried by a high-frequency carrier is not only diminished by the parasitics of the semiconductor technology but also hindered by natural phenomena in our environment. While improving semiconductor technology and the radio propagation channel are beyond the scope of this thesis, this work presents an architecture and design methodology of radio frequency integrated circuits (RFICs) to enhance the efficiency of signal transmission within the radio receiver front-end.
Parasitics of semiconductor technology are highly dependent on the frequency of operation and the layout of signal paths. Once the frequency of the carrier signal and the type of semiconductor technology are decided, the entire effort lies in the layout of the path on this semiconductor technology. It consists of strategically placing various building blocks, with different circuit operations, referred to as architecture design, and the choice of an appropriate arrangement of semiconductor devices, known as circuit topology. The sensitivity and efficiency of the radio receiver are determined by the architectural choices, circuit topologies, and their interconnections. In this work, a judicious selection of a receiver front-end architecture, circuit topologies, and layout strategies leads to a highly efficient receiver front-end at 300 GHz. The reader of this thesis will undoubtedly recognize the significant technological milestone achieved in this work, which contributes to the advancement of 6G radio implementation.
With the support of the Academy of Finland’s 6G Flagship Program, we have successfully implemented a radio receiver front-end operating at 300 GHz, paving the way for ultra-high-speed wireless communication.
This thesis represents an endeavor to implement a radio operating at 300 GHz. Why at such a high frequency? Because the higher the frequency, the more bandwidth is available to facilitate ultra-high-speed radio communication. The focus of this work is the design of the front-end of the radio receiver, which is a fascinating fusion of analog circuit theory, microwave theory, and radio frequency engineering. Utilizing the fundamentals of these three domains, I approached the design of the receiver’s front-end.
Modern highly integrated radios are designed using semiconductor technologies. In a typical radio system, information travels through semiconductor material and the atmosphere. Information carried by a high-frequency carrier is not only diminished by the parasitics of the semiconductor technology but also hindered by natural phenomena in our environment. While improving semiconductor technology and the radio propagation channel are beyond the scope of this thesis, this work presents an architecture and design methodology of radio frequency integrated circuits (RFICs) to enhance the efficiency of signal transmission within the radio receiver front-end.
Parasitics of semiconductor technology are highly dependent on the frequency of operation and the layout of signal paths. Once the frequency of the carrier signal and the type of semiconductor technology are decided, the entire effort lies in the layout of the path on this semiconductor technology. It consists of strategically placing various building blocks, with different circuit operations, referred to as architecture design, and the choice of an appropriate arrangement of semiconductor devices, known as circuit topology. The sensitivity and efficiency of the radio receiver are determined by the architectural choices, circuit topologies, and their interconnections. In this work, a judicious selection of a receiver front-end architecture, circuit topologies, and layout strategies leads to a highly efficient receiver front-end at 300 GHz. The reader of this thesis will undoubtedly recognize the significant technological milestone achieved in this work, which contributes to the advancement of 6G radio implementation.
With the support of the Academy of Finland’s 6G Flagship Program, we have successfully implemented a radio receiver front-end operating at 300 GHz, paving the way for ultra-high-speed wireless communication.
Last updated: 30.5.2024