Efficient Hardware Architectures for Multi-Kernel Polar Codes
Thesis event information
Date and time of the thesis defence
Place of the thesis defence
L10 lecture hall
Topic of the dissertation
Efficient Hardware Architectures for Multi-Kernel Polar Codes
Doctoral candidate
M.Sc. (Tech.) Hossein Rezaei
Faculty and unit
University of Oulu Graduate School, Faculty of Information Technology and Electrical Engineering, Centre for Wireless Communications - Radio Technologies (CWC-RT)
Subject of study
Doctoral Programme in Telecommunications Engineering
Opponent
Professor Jyri Hämäläinen, Aalto University
Custos
Professor Premanandana Rajatheva, University of Oulu
Efficient Hardware Architectures for Multi-Kernel Polar Codes
This thesis focuses on designing innovative and optimized hardware architectures for both the encoding and decoding of multi-kernel polar codes, with an emphasis on improving latency, throughput, and resource utilization.
Key contributions of the research include:
• A novel multi-kernel (MK) decoder architecture based on the fast-simplified successive cancellation (fast-SSC) algorithm, offering flexibility in code length, rate, and kernel sequence, and significantly reducing latency.
• The design of an unrolled architecture for systematic and non-systematic MK polar codes, along with two stage-folded encoders for dynamic kernel assignment, supporting 83 different codes with varying trade-offs between throughput and resource consumption.
• A high-throughput, rate-flexible combinational architecture for MK polar decoding, allowing a new code rate to be assigned at every clock cycle.
• A Python-based compiler that automates the generation of HDL modules for FPGA implementation of both encoder and decoder architectures.
This work presents state-of-the-art advancements in the field of error-correcting codes and provides efficient and flexible solutions for modern communication systems.
Key contributions of the research include:
• A novel multi-kernel (MK) decoder architecture based on the fast-simplified successive cancellation (fast-SSC) algorithm, offering flexibility in code length, rate, and kernel sequence, and significantly reducing latency.
• The design of an unrolled architecture for systematic and non-systematic MK polar codes, along with two stage-folded encoders for dynamic kernel assignment, supporting 83 different codes with varying trade-offs between throughput and resource consumption.
• A high-throughput, rate-flexible combinational architecture for MK polar decoding, allowing a new code rate to be assigned at every clock cycle.
• A Python-based compiler that automates the generation of HDL modules for FPGA implementation of both encoder and decoder architectures.
This work presents state-of-the-art advancements in the field of error-correcting codes and provides efficient and flexible solutions for modern communication systems.
Last updated: 14.10.2024